Fast localization of electrical failures on an integrated circuit system and method

ABSTRACT

Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize defects on the test chip.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/432,786, filed Dec. 11, 2002, the entire content of which isincorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present application relates to fast localization of electricalfailures on an integrated circuit.

2. Related Art

The fabrication of integrated circuits is an extremely complex processthat may involve hundreds of individual operations. For a number ofreasons, defects can be introduced into the integrated circuits duringthese operations. For example, in photoresist and photomask operations,the presence of contaminants such as dust, minute scratches and otherimperfections in the patterns on the photomasks can produce defectivepatterns on the semiconductor wafers, resulting in defective integratedcircuits.

Defective integrated circuits may be identified both by visualinspection under high magnification and by electrical tests. Once adefective integrated circuit has been identified, the location of thedefect in the integrated circuit is typically determined to permitcloser inspection of the defect. Conventional techniques for detectingand localizing the defects typically test integrated circuitsindividually, which can be time consuming, particularly when the numberof integrated circuits being tested is large.

SUMMARY

In one exemplary embodiment, fast localization of electrically measureddefects of integrated circuits includes providing information forfabricating a test chip having test structures configured for parallelelectrical testing. The test structures on the test chip areelectrically tested employing a parallel electrical tester. The resultsof the electrical testing are analyzed to localize defects on the testchip.

DESCRIPTION OF DRAWING FIGURES

The present application can be best understood by reference to thefollowing description taken in conjunction with the accompanying drawingfigures, in which like parts may be referred to by like numerals:

FIG. 1 is a flow diagram of an exemplary process of localizing defectson a test chip;

FIG. 2 is a flow diagram of another exemplary process of localizingdefects on a test chip;

FIG. 3 is a flow diagram of another exemplary process of localizingdefects on a test chip;

FIG. 4 is a block diagram of an exemplary system to localize defects ona test chip;

FIG. 5 depicts a product chip with design pattern variations;

FIG. 6 depicts an exemplary layout of a test chip;

FIG. 7 depicts an exemplary padgroup;

FIGS. 8 and 9 depict exemplary test structures;

FIG. 10 depicts another exemplary padgroup;

FIGS. 11, 12-A, 12-B, and 12-C depict exemplary test structures;

FIG. 13 depicts another exemplary padgroup.

FIGS. 14-21 depict portions of another exemplary layout;

FIG. 22 depicts another exemplary layout;

FIG. 23 is a front view of an exemplary parallel tester;

FIG. 24 is a side of the exemplary parallel tester depicted in FIG. 23;

FIG. 25 is a top view of an exemplary wafer tester system;

FIG. 26 is a perspective view of the exemplary wafer tester systemdepicted in FIG. 25;

FIG. 27 is a system block diagram of the wafer tester system depicted inFIG. 25;

FIG. 28 is a system block diagram of a portion of the wafer testersystem depicted in FIG. 25;

FIG. 29 is a circuit diagram of a resistor divider;

FIG. 30 is a circuit diagram of a two point resistance measurementimplementation;

FIG. 31 is a system block diagram of a portion of a switch card;

FIG. 32 is a circuit diagram of a portion of a pin terminator circuit;

FIG. 33 is a system block diagram of a measurement control (MC) unit;

FIG. 34 depicts an exemplary process of defect analysis; and

FIGS. 35, 36, and 37 depict exemplary plots of failure rate vs. layoutbins;

DETAILED DESCRIPTION

The following description sets forth numerous specific configurations,parameters, and the like. It should be recognized, however, that suchdescription is not intended as a limitation on the scope of the presentinvention, but is instead provided as a description of exemplaryembodiments.

I. Overview

With reference to FIG. 1, in one exemplary embodiment, a process oflocalizing defects on a test chip is depicted. As will be describedbelow in greater detail, a test chip includes a plurality of teststructures, which are designed to simulate failure modes that may resultin fabricating an integrated circuit of an actual product chip.

In block 102, a test chip is fabricated on a test wafer. The test chipincludes a plurality of test structures and probe pads. A test structureis electrically connected to one or more probe pads, which are used toelectrically test the test structure.

In one exemplary embodiment, the test structures of the test chip areconfigured for parallel electrical testing. More specifically, teststructures are grouped together as one or more padgroups. The teststructures in a padgroup are electrically tested in parallel, meaningthat the test structures are electrically tested together atapproximately the same time.

In another exemplary embodiment, the test structures of the test chipare configured for localization of defects. More specifically, if a teststructure on a test chip is fabricated with a defect that results in thetest structure failing the electrical test performed on the teststructure, the location of the test structure with the defect within thetest chip is obtained.

In block 104, the test structures on the test chip are electricallytested in parallel. In one exemplary embodiment, the test structures ina padgroup are electrically tested in parallel, meaning that they areelectrically tested together at approximately the same time.Additionally, multiple padgroups can be electrically tested in parallel.Thus, in this manner, the amount of time required to electrically testthe test structures on the test chip may be reduced.

In block 106, the results of the electrical test performed on thefabricated test chips are analyzed. More specifically, a test structurethat fails the electrical test is assumed to have been fabricated with adefect. Thus, the electrical test detects defects on the test chip. Inone exemplary embodiment, the detected defects are classified as randomor systematic defects. Additionally, in one exemplary embodiment, when atest structure with a defect is identified, the location of the teststructure within the test chip is obtained.

It should be noted that the exemplary process described above anddepicted in FIG. 1 can include various additional steps. For example,with reference to FIG. 2, in one alternative embodiment, in block 202,the fabricated chip can be in-line inspected. More specifically, thefabricated chip can be in-line inspected using an optical inspectiontool, such as a microscope, to visually detect any defects on thefabricated test chip and to determine the location of the defects. Asdepicted in FIG. 2, the results of the analysis performed in block 106can be used as a feedback to the in-line inspection performed in block202.

With reference to FIG. 3, in another alternative embodiment, in block302, the results of the analysis performed in block 106 can be used toinspect the defects using an inspection tool, such as an opticalinspection tool, a defect review scanning electron microscope (DR-SEM),a wafer inspection scanning electron microscope (SEM), and the like.More specifically, the results of the electrical test can localize(i.e., identify the location of) the test structure with a defect withinthe test chip. The inspection tool can then inspect the test structureto localize the defect to a specific location within the test structure.The inspection tool can also obtain an image of the defect, which canthen be used to further analyze the defect, such as measuring the sizeof the defect, classifying the defect, and identifying a potential causeof the defect. It should be recognized that block 202 can be omittedfrom the present exemplary embodiment.

In this alternative embodiment, the test chip is adapted for use withthe inspection tool. More specifically, the test structures on the testchip are sized to be compatible with the capabilities of an inspectiontool, such as the view field of the inspection tool, which determinesthe area that can be inspected at one time, and the resolution of theinspection tool, which determines the amount of detail that can beobtained. For example, when a test structure is larger than the viewfield, the inspection tool may need to scan the test structure in orderto locate (i.e., localize) a defect within the test structure. When atest structure is smaller than the view field, the level of detail thatis provided by the inspection tool may be reduced.

With reference to FIG. 4, an exemplary system of localizing defects on atest chip is depicted. More specifically, in one exemplary embodiment, adefect localization system 400 includes a fabrication facility 404, anin-line inspection tool 406, a parallel electrical tester 408, aprocessor 410, and an inspection tool 412.

In the present exemplary embodiment, a test wafer 402 with one or moretest chips is fabricated in fabrication facility 404. The test wafer 402is in-line inspected using in-line inspection tool 406. The test wafer402 is parallel electrically tested using parallel electrical tester408. The results of the electrical test can be analyzed using processor410. It should be recognized that processor 410 can be a component ofparallel electrical tester 408 or a separate unit. The test wafer 402 isinspected using inspection tool 412.

It should be recognized that system 400 can include additional elementsor fewer elements. For example, in-line inspection tool 406 can beomitted from system 400. Alternatively and/or additionally, inspectiontool 412 can be omitted from system 400.

II. Test Chip

A test chip is used to characterize integrated circuit layout andmanufacturing process interactions of an actual product chip. Asdescribed above, a test chip is designed to simulate the same failuremodes as an actual product chip.

More specifically, as conceptualized in FIG. 5, an actual product chip502 can have a plurality of design pattern variations. For example, onedesign pattern variation can include lines of a certain line width. Asdepicted in FIG. 5, the design pattern variations can include a numberof core design pattern variations 504. A test chip 506 can be designedto include these core design pattern variations. Test chip 506 is easierto inspect, test, and analysis than actual product chip 502. In thecontext of the present description, the design pattern variations on atest chip are referred to as experiments. Additionally, a test chip canalso be referred to as a CHARACTERIZATION VEHICLE, which is a trademarkof PDF Solutions of San Jose, Calif. USA.

The following table lists exemplary test structures: Name DescriptionComments Via Chain without Vertical or horizontal snaking May be wiredout in Neighborhood chain of M1, M2 links connected “long runner” byvias configuration Via Chain with Vertical or horizontal snakingNeighborhood chain of M1, M2 links connected by vias 1-D SnakeCombVertical or horizontal metal lines May have either parallel BigCellarranged in a “grating.” Edge or perpendicular patterns hookups createsnake between in underlayer two interleaved combs 1-D SnakeComb withVertical or horizontal metal lines May have either parallel SubCellsarranged in a “grating.” Edge or perpendicular patterns hookups createsnake between in underlayer two interleaved combs. Many such SnakeComb“sub cells” arranged in an array Snake Vertical or horizontal metallines May have either parallel arranged in a “grating.” Edge orperpendicular patterns hookups create a pure snake in underlayer 1-DComb Vertical or horizontal metal lines May have either parallelarranged in a “grating.” Edge or perpendicular patterns hookups createtwo interleaved in underlayer combs. Important area is long lines andline ends may be relaxed 2-D Comb Like many 1-D combs appended Nearlyidentical patterns vertically or horizontally. in underlayer Importantarea is line end rather than long lineIt should be recognized, however, that the types and numbers of teststructures on a test chip may vary.

As described above, in one exemplary embodiment, the test structures ofa test chip are configured for parallel electrical testing. Withreference to FIG. 6, an exemplary layout 602 of a test chip is depicted.Layout 602 includes a plurality of padgroups 604 arranged in rows andcolumns. More specifically, FIG. 6 depicts 240 padgroups arranged in 12rows and 20 columns. It should be noted, however, that any number ofpadgroups may be arranged in any number of rows and columns.Additionally, FIG. 6 depicts padgroups having a width of 1080 micronsand a height of 1800 microns. It should be noted, however, that apadgroup may have any width and height.

As further depicted in FIG. 6, a padgroup 604 includes a plurality oftest structures 606 and a padframe 608 with electrical probe pads 610for the test structures 606 within padgroup 604. More specifically,padgroup 604 includes padframe 608 disposed between two columns of teststructures 606 within padgroup 604.

As described above, in one exemplary embodiment, the test structureswithin a padgroup are electrically tested in parallel, meaning that thetest structures within the padgroup are electrically tested together atapproximately the same time. Thus, in padgroup 604 depicted in FIG. 6,test structures 606 within padgroup 604 are electrically testedtogether. Additionally, multiple padgroups 604 may be electricallytested together. For example, in one exemplary embodiment, six padgroups604 are electrically tested together at one time.

Test structures 606 are electrically tested using a parallel tester thathas a plurality of test probes that make electrical contact with probepads 610 within padframe 608. More specifically, for padgroup 604 inFIG. 6, 32 test probes contact the 32 probe pads in padframe 608 toelectrically test the 30 test structures in padgroup 604 in parallel.

The arrangement of probe pads for test structures within a padgroup intoa padframe for the padgroup facilitates parallel testing of the teststructures. Additionally, locating probe pads adjacent to teststructures reduces the length of the interconnection lines between theprobe pads and the test structures.

By parallel testing the test structures, the size of the test structurescan be decreased and/or the number of test structures on a test chip canbe increased without necessarily increasing the overall time toelectrically test the test chip. In turn, by decreasing the size of thetest structures, a defect on the test chip can be located to a morespecific location (i.e., localized) on the test chip. Additionally, inan exemplary embodiment when an inspection tool is used, the teststructures can be sized to be compatible with the capabilities of theinspection tool, such as the view field and resolution of the inspectiontool.

In FIG. 6, a padgroup 604 is depicted with test structures 606 that aretwo-terminal test structures (e.g., via chains, via combs, metal snakes,metal combs, and the like). Additionally, in FIG. 6, test structures 606have one common terminal. In one exemplary embodiment, the commonterminal can be grounded to the substrate.

FIG. 7 provides exemplary dimensions of test structures 606 and padframe608 of padgroup 604 having 28 or 30 two-terminal test structures ordevices under test (DUT's). In the present exemplary embodiment, forpadframe 608, the pad size is 80 microns. The pad pitch in the verticaldirection (Ypitch) is 100 microns. The pad pitch in the horizontaldirection (Xpitch) is 130 microns. The width is 210 microns. The heightis 1580 microns. For test structure 606, the height is 80 microns, andthe width is 380 microns. The test structure types are snakes, combs, orany other two-terminal devices. The pads at the bottom of the columnsare common nodes. The next row of pads may be used for neighborhoodmetals connections (to check for shorts to neighborhood). There are 30DUTs per padgroup. It should be recognized, however, that thesedimensions may vary.

In FIG. 8, test structures 606 in padgroup 604 of FIG. 7 are depicted asbeing configured as 28 via chains. Alternatively, in FIG. 9, teststructures 606 in padgroup 604 of FIG. 7 are depicted as 30 comb cells.

It should be recognized, however, that test structures 606 in padgroup604 of FIG. 7 can be configured as various two-terminal test structures.Additionally, it should be recognized that a padgroup 604 can includetest structures having any number of terminals.

For example, in FIG. 10, a padgroup 604 is depicted with eight teststructures 606 that are four-terminal test structures or devices undertest (DUT's). It should be noted, however, that padgroup 604 can includeany number of four-terminal test structures. In the present exemplaryembodiment, for padframe 608, the pad size is 80 microns. The pad pitchin the vertical direction (Ypitch) is 100 microns. The pad pitch in thehorizontal direction (Xpitch) is 130 microns. The width is 210 microns.The height is 1580 microns. For test structure 606, the height is 380microns, and the width is 380 microns. The test structure types aresnakecombs or any other four-terminal devices. There are eight DUTs perpadgroup. It should be recognized, however, that these dimensions canvary.

In FIG. 11, test structures 606 in padgroup 604 of FIG. 10 are depictedas being configured as eight snakecomb cells. In one exemplaryembodiment, each snakecomb cells depicted in FIG. 11 is configured topermit localization of a defect in a snakecomb cell to a location withinthe snakecomb cell.

More specifically, with reference to FIG. 12-A, assume a snakecomb cell1202 has terminals N, C, and G. With reference to FIG. 12-B, assume nowthat snakecomb cell 1202 has a defect 1204. With reference to FIG. 12-C,assume that the snake comb with the defect depicted in FIG. 12-C can becharacterized by electric circuit 1206.

In one exemplary embodiment, the following electrical test can beperformed:

R_(gn)=force 1V at G, terminate at N, measure resistance GN

R_(gc)=force 1V at G, terminate at C, measure resistance GC

R_(nc)=force 1V at N, terminate at C, measure resistance NCwhere A, B, and D are calculated as follows:$D = \frac{R_{gc} - \left( {R_{gn} - R_{nc}} \right)}{2}$ B = R_(gc) − DA = R_(gn) − Band:

shortPerc (position of defect on Snake vs. Grounded side of Snake$\left. (G) \right) = {\frac{A}{R_{gn}}.}$

Alternative, assume the following electric tests are performed:

R_(gn)=force 1V at G, terminate at N, measure resistance GN

R_(gc)=force 1V at G, terminate at C, measure resistance GC

R_(ngc)=force 1V at N, terminate at C, measure resistance NC(R_(ngc) differs from the previous measurement method because it forces1V at both G and N to cut off a sneak path between the G terminals ofmultiple snakecombs in the same padgroup.) where A, B, and D arecalculated as follows:$X = \frac{R_{gn} - \left( {R_{gc} - R_{ngc}} \right)}{2}$$B = \sqrt{\left( R_{gn} \right)^{2} - {R_{gn}X}}$ A = R_(gn) − Band:

-   -   shortPerc (position of defect on Snake vs. Grounded side of        Snake $\left. (G) \right) = {\frac{A}{R_{gn}}.}$

In one exemplary embodiment, a soft short is detected by comparing aline resistance, which can be determined based on a measured voltage, toa threshold resistance. If the line resistance is below the thresholdvoltage, then a soft short is detected. A hard short is also detected bycomparing a line resistance to a threshold resistance. However, thethreshold resistance used to detect a soft short is greater than thethreshold resistance used to detect a hard short.

Additionally, in another exemplary embodiment, a soft short is detectedby determining an average resistance for a number of lines that areadjacent to each other, such as those within the same padgroup. If aparticular line has a resistance less than the average resistance by aspecified amount, then a soft short is detected. A hard short is alsodetected by comparing a line resistance to the average resistance.However, the specified amount of difference between the resistance of aline with a soft short and the average resistance is less than thedifference between the resistance of a line with a hard short and theaverage resistance.

In FIG. 13, another padgroup 604 is depicted with eight test structures606 that are four-terminal test structures or devices under test(DUT's). In contrast to padgroup 604 depicted in FIG. 10, padgroup 604depicted in FIG. 13, 4 test structures 606 are formed in one layer andfour test structures 606 are formed on another layer. In the presentexemplary embodiment, for padframe 608, the pad size is 80 microns. Thepad pitch in the vertical direction (Ypitch) is 100 microns. The padpitch in the horizontal direction (Xpitch) is 130 microns. The width is210 microns. The height is 1580 microns. For test structure 606, theheight is 760 microns, and the width is 380 microns. The test structuretypes are snakecombs or any other four-terminal devices. There are eightDUTs per padgroup with 4 in each layer. Padgroup 604 has the sameschematic as padgroup 604 in FIG. 10. It should be recognized, however,that these dimensions may vary. Additionally, it should be recognizedthat test structure can be formed on any number of metal layers, wherethe test structure below another test structures in another layer can betested, and the interaction of test structures at two or levels can bemeasured.

In FIG. 14, a portion of an exemplary layout 602 is depicted with aplurality of padgroups 604 arranged in rows and columns. As describedabove, in one exemplary embodiment, six padgroups 604 can beelectrically tested together at one time. In the exemplary embodimentdepicted in FIG. 14, a stick 1402 labeled as “2×106 prgxx stick” in FIG.14 includes padgroups 604 labeled as 1, 2, 3, 4, 5, and 6. In thepresent exemplary embodiment, padgroups 604 in stick 1402 areelectrically tested together with a probe card from a parallelelectrical tester.

As depicted in FIG. 14, in the present exemplary embodiment, eachpadgroup 604 includes eight test structures 606. Each padgroup 604 alsoincludes four pads for each test structure 606. Thus, the padframe foreach padgroup 604 includes a total of 32 pads.

As also depicted in FIG. 14, layout 602 also includes five minipadchkcells 1404 disposed between padsgroups 604 at locations labeled a, b, c,d, and e. As will be described in more detail below, each minipadchkcell 1404 includes two test structures with four pads, which arearranged as a 2×2 padframe.

Thus, stick 1402 includes a total of 212 pads ((32 pads/padgroup×8padgroups)+(4 pads/minipadchk cell×5 minipadchk cells)). As depicted inFIG. 14, the 212 pads are arranged in two adjacent columns. Thus, thepadframe for stick 1402, which includes the padframe from padgroups 604and the pads from minipadchk cell 1404, is a 2×106 padframe. In thepresent exemplary embodiment, the padframe width is 210 microns.

In the present exemplary embodiment, stick 1402 is referenced using twoparameters (prgname and prgrow). The progName parameter uniquelyidentifies each stick 1402 in layout 602, and the progrow parameteruniquely identifies each padgroup 604 within a stick 1402. Moreparticularly, the parameter prgxxx is used to refer to a stick 1402. Fora layout with one or two metal layers (i.e., M1/M2), two digits are used(e.g., prgxx). For a layout with three metal layers (i.e., M3), threedigits are used (e.g., prog3xx). In the present exemplary embodiment,the parameter prg00 is reserved for use as a continuity pad check stick.The progamne and progRow parameters can be exported as a text file. Itshould be recognized that the use of these parameters is exemplary andthat various parameters can be used to reference stick 1402 and thecomponents within stick 1402.

With reference to FIG. 15, in the present exemplary embodiment, stick1402 has a floorplan height specification of 10.72 millimeters. Moreparticularly, as depicted in FIG. 15, a height H1 includes spacing forbottom routing. A height H2 includes the overall height of thecomponents within stick 1402. A height H3 includes spacing for labelsand M3 virtual ground pads. In the present exemplary embodiment, H1, H2,and H3 are 15 microns, 10,580 microns, and 125 microns, respectively,for a total of 10,720 microns or 10.72 millimeters. It should berecognized that these dimensions are exemplary and that stick 1402 canhave various floorplan height specifications.

With reference to FIG. 16, the top of height H1 is defined by the bottomedge of pads 16 and 32 of padgroup 604 labeled 1 in FIG. 14. The bottomof height H1 includes a buffer zone for butting another stick 1402 (FIG.14). In one exemplary embodiment, the buffer zone is also required forVIA experiment routing. As described above, in one exemplary embodiment,height H1 is 15 microns.

With reference to FIG. 17, height H2 (FIG. 15) includes height H2 a ofpadgroup 604. The top of height H2 a is defined by the top edge of pads1 and 17 of padgoup 604. The bottom of height H2 a is defined by thebottom edge of pads 16 and 32 of padgroup 604. In the present exemplaryembodiment, the pad size is 80 microns×80 microns. The pad pitch in thevertical direction (Ypitch) is 100 microns. The pad spacing in thevertical direction (Yspace) is 20 microns. Thus, height H2 a is 1,580microns ((16 pads×80 microns/pad)+(15 spacings×20 microns/spacing)).

With reference to FIG. 18, height H2 (FIG. 15) also includes height H2 bof minipadchk 1404. As described above and depicted in FIG. 18,minipadchk 1404 includes two test structures 1802 with four pads, whichare arranged as a 2×2 padframe. In the present exemplary embodiment,test structures 1802 are used to verify the operation of the probe cardand the associated test system. The top of height H2 b is defined by theedge of pads 16 and 32 of the padgroup above minipadchk 1404. The bottomof height H2 b is defined by the edge of pads 1 and 17 of the padgroupbelow minipadchk 1404. In the present exemplary embodiment, the pad sizeis 80 microns×80 microns. The pad pitch in the vertical direction(Ypitch) is 100 microns. The pad spacing in the vertical direction(Yspace) is 20 microns. Thus, height H2 b is 220 microns ((2 pads×80microns/pad)+(3 spacings×20 microns/spacing)).

With reference to FIG. 19, height H2 includes the dimensions of eachpadgroup (i.e., height H2 a) and minipadchk (i.e., height H2 b). The topof height H2 is defined by the top edge of pads 1 and 17 of the toppadgroup labeled 6 in FIG. 19. The bottom edge of height H2 is definedby the bottom edge of pads 16 and 32 of the bottom padgroup labeled 1 inFIG. 19. In the present exemplary embodiment, the pad size is 80microns×80 microns. The pad pitch in the vertical direction (Ypitch) is100 microns. The pad spacing in the vertical direction (Yspace) is 20microns. Thus, height H2 is 10,580 microns ((6 padgroups×1,580micron/padgroup)+(5 minpadchk×220 microns/minipadchk)).

With reference to FIG. 20, height H3 includes height H3 a, height H3 b,and height H3 c. The top of height H3 is defined by the bottom edge ofthe next metal structure. The bottom of height H3 is defined by the topedge of pads 1 and 17 of the top padgroup labeled 6 in FIG. 19.

The top of height H3 a is defined by the top edge of the label. Thebottom of height H3 a is defined by the top edge of pads 1 and 17 of thetop padgroup labeled 6 in FIG. 19. In one exemplary embodiment, thelabel height is 18 microns. The spacing from routing lines to the bottomof the label is 10 microns. In the present exemplary embodiment, heightH3 a is 28 microns.

The top of height H3 b is defined by the top edge of the M3 virtualground pad. The bottom of height H3 b is defined by the top edge of thelabel. In one exemplary embodiment, the pad height is 80 microns. Thespace from the label top to the bottom of the M3 virtual ground pad is14 microns. In the present exemplary embodiment, height H3 b is 94microns.

The top of height H3 c is defined by the bottom edge of the next metalstructure. The bottom of height H3 c is defined by the top edge of theM3 virtual ground pad. Height H3 c functions as a buffer zone. In thepresent exemplary embodiment, height H3 c is 3 microns. Thus, height H3is 125 microns (28 microns+94 microns+3 microns).

With reference to FIG. 21, in one exemplary embodiment, layout 602 (FIG.14) includes a height H4 for stacking sticks 1402 (FIG. 14). The top ofheight H4 is defined by the bottom edge of pads 16 and 32 of the bottompadgroup in the upper stick in the stack. The bottom of height H4 isdefined by the top edge of pads 1 and 17 of the top padgroup in thelower stick in the stack. In one exemplary embodiment, height H4 issized to fit a minipadchk 1404 (FIG. 14), which allows for minipadchk1404 (FIG. 14) to be included between the bottom padgroup in the topstick in the stack and the top padgroup in the lower stick in the stack.Thus, height H4 is equal to height H2 a of 220 microns. Additionally, asdepicted in FIG. 21, height H4 a is the difference between height H4 andheight H1 and H3 (i.e., H4−H1−H3), which is 80 microns.

With reference to FIG. 22, an exemplary layout 602 configured fordeployment into a stepper square field is depicted. Layout 602 includesa stack of two sticks 1402 with height H4 a between sticks 1402. Thus,in the present exemplary embodiment, the total field height of layout602 is 21.52 millimeters (10.72 millimeters+0.08 millimeters+10.72millimeters).

It should be recognized, however, that layout 602 can be configured forvarious dimensions. For example, layout 602 can be configured fordeployment into a scanner rectangular field. A typical scanner field hasa width (X) of 26 millimeters and a height (Y) of 32 millimeters. Thus,layout 602 can include a stack of three sticks 1402. In the presentexemplary embodiment, the total field height would be 32.32 min ((10.72millimeters/stick×3 sticks)+(0.08 millimeters/spacing×2 spacings)).

To better fit the height of a typical scanner field, various adjustmentscan be made to layout 602 to reduce overall height. For example, heightH4 a can be reduced from 80 microns to 10 microns. Thus, the total fieldheight of layout 602 is reduced to 32.18 millimeters ((10.72millimeters/stick×3)+(0.01 millimeters/spacing×2 spacings)).

Alternatively, with reference to FIG. 20, the M3 virtual ground pad canbe redesigned into a rectangular shape having a width and height of 40microns×160 microns, which reduces the height H3 b from 94 microns to 45microns. Height H3 is reduced to 76 microns, which reduces the height ofa stick to 10.671 millimeters. Thus, with reference again to FIG. 22,the total field height of layout 602 is reduced to 32.033 millimeters((10.671 millimeters/stick×3)+(0.08 millimeters/spacing×2 spacings)).The reduced size of the M3 virtual ground pad remains large enough foran SEM inspection tool, such as the SEMVision tool produced by AppliedMaterials, Inc. of Santa Clara, Calif., USA, to focus an electron beamto inspect/view the M3 virtual ground pad for defect localization.

As another alternative, four of the five minipadchks can be removed.More particularly, with reference to FIG. 14, the minipadchks labeled a,b, d, and e are removed, and only the minpadchk in the center, which islabeled c, is retained. Thus, height H2 is reduced to 9,700 microns,which reduces the height of a stick to 9.791 millimeters. Thus, withreference again to FIG. 22, the total field height of layout 602 isreduced to 29.393 millimeters ((9.791 millimeters/stick×3)+(0.01millimeters/spacing×2 spacings)). Note that a different probe card isused to test this shorter stick.

It should be noted, however, that the various dimensions provided aboveare exemplary, and any one or more of these dimensions may be varied.Additionally, it should be recognized that the number of pads, teststructures, padgroups, sticks, and levels can be varied.

III. Parallel Electrical Tester

As described above, the test structures within a padgroup are testedtogether using a parallel electrical tester. With reference to FIG. 23,an exemplary parallel electrical tester 2300 is depicted. In oneexemplary embodiment, tester 2300 performs automated resistancemeasurement and leakage current measurements.

In the present exemplary embodiment, tester 2300 is designed to enabletesting of structures within die on a wafer in less than one hour, whichis a speedup of 10-20 times as compared to conventional parametrictesting approaches. Tester 2300 also includes the following features:

-   -   256 identical, independent, parallel I/O channels, each with the        following capabilities: voltage and resistance measurement,        source voltage or source current, and programmable pin        termination;    -   Resistance measurement capability from 10 ohm to 100 Mohm;    -   Cable-out interface to prober/prober tester interface (PTI) (8        cables with 32 signals/cable);    -   Standard general purpose interface bus (GPIB) interface to        compatible wafer probers;    -   PC-based controller with Microsoft Windows 2000 Operating        System;    -   Emergency Off (EMO) switches with EMO daisy-chain connections on        rear panel;    -   Rolling casters for ease of movement;    -   Leveling feet for secure tester installation; and    -   Clean room compatible design.        It should be recognized that these features are exemplary, and        that any one or more of these features can be omitted from        tester 2300, or any one or more additional features can be        included in tester 2300.

As depicted in FIGS. 23 and 24, tester 2300 includes a monitor 2302, akeyboard 2304, a measurement control (MC) unit 2306, casters 2308, andEMO 2310. MC unit 2306 includes a pin termination module 2314, a fantray 2316, a data acquisition (DAQ) module 2318, and a tester controlmodule 2320. DAQ module 2318 includes digital I/O pin terminationcontrol, current/voltage sources, and voltage measurement units. Itshould be recognized, however, that tester 2300, MC unit 2306, and DAQmodule 2318 can include fewer or additional components.

With reference to FIGS. 25 and 26, an exemplary wafer tester system 2500is depicted. In one exemplary embodiment, tester system 2500 includesparallel electrical tester 2300, wafer prober 2502, and wafer loader2504. As depicted in FIGS. 25 and 26, tester 2300 is connected to aprober tester interface (PTI) 2506 on wafer prober 2502 using cables2508. In the present exemplary embodiment, cables 2508 are preferably1.8 meters long and connected to the upper rear panel of MC unit 2306(FIG. 23). As depicted in FIGS. 25 and 26, tester 2300 is preferablypositioned close enough to wafer prober 2502 to reduce strain on cables2508. Ideally, as depicted in FIGS. 25 and 26, tester 2300 isimmediately adjacent to wafer prober 2502. Wafer loader 2504 includesone or more front opening unified pods (FOUPs) to process multiplewafers through wafer prober 2502.

With reference to FIG. 27, a system block diagram is depicted of testersystem 2500. As depicted in FIG. 27, wafer prober 2502 includes anauto-loader 2704 to receive a test wafer 2702 from wafer loader 2504(FIGS. 25 and 26). Wafer prober 2502 also includes a probe card 2706 toelectrically contact test wafer 2702. More particularly, in the presentexemplary embodiment, probe card 2706 includes 256 pins. Thus, the 212pads in stick 1402 (FIG. 14) can be electrically tested in parallel atone time using probe card 2706.

In the present exemplary embodiment, wafer prober 2502 is controlled bytester control module 2320 through GPIB interface 2708. Moreparticularly, tester control module 2320 issues commands to wafer prober2502, such as commands to position probe card 2706, lift probe card 2706off of a stick, move to a new position, and descend to make contact withanother stick.

As depicted in FIG. 27, in the present exemplary embodiment, testsignals are transmitted between probe card 2706 and pin terminationmodule 2314 through a signal bus 2716. In the present exemplaryembodiment, signal bus 2716 is an 8×32 signal bus. The test signals arealso transmitted between termination module 2314 and multiplexer module2710 through signal bus 2716. The test signals are then transmitted frommultiplexer module 2710 to DAQ module 2318.

As also depicted in FIG. 27, MC unit 2306 sends digital control signalsto pin termination module 2314 through a digital I/O (DIGIO) 2712. MCunit 2306 also includes analog voltage sources for pin terminationmodule 2314. Additionally, MC unit 2306 and tester control module 2320are connected using a peripheral component interconnect (PCI) bridge2714.

With reference to FIG. 28, a system block diagram of a portion oftermination module 2314 (FIG. 27) is depicted. As depicted in FIG. 28,termination module 2314 (FIG. 27) includes a plurality of switch cards2802, which receive test signals from probe card 2706. In the presentexemplary embodiment, termination module 2317 (FIG. 27) includes 8switch cards 2802, where each switch card can be connected to as many as32 pins from probe card 2706. More particularly, as depicted in FIG. 28,pins 1-32 from probe card 2706 are connected to a first switch card 2802(labeled PT1 in FIG. 28), subsequent groups of 32 pins are connected tosubsequent switch cards 2802, and then pins 225-256 are connected to aneighth switch card 2802 (labeled PT8 in FIG. 28).

As also depicted in FIG. 28, each switch card 2802 is connected to DIGIO2712 (FIG. 27) and voltage sources in MC unit 2306 (FIG. 27). Moreparticularly, each switch card 2802 is connected to 16 DIGIO lines and 2voltage sources.

In the present exemplary embodiment, one function of termination module2314 (FIG. 27), and more particularly switch card 2802, is to form aresistor divider with the resisters in the device under test (DUT),selectable on-board termination resistor, and software-controlled analogvoltage sources. More particularly, with reference to FIG. 29, anexemplary circuit diagram is depicted. As depicted in FIG. 29, aresistor divider is formed with the resistor R in the DUT, thetermination resistor RT, and the analog voltage source Vs. Thus, theresistance of the DUT can be determined from voltage measures V_(M).Note that the DUT current (IDUT) is equal to V_(M)/V_(T), the DUTvoltage is equal to V_(S)−V_(M), and the DUT resistance (R_(DUT)) isequal to V_(DUT)/I_(DUT). Additionally, in the present exemplaryembodiment, resisters R_(W) are only used for error calculations ofabsolute R value.

With reference to FIG. 30, an exemplary circuit diagram of a two pointresistance measurement implementation is depicted. As depicted in FIG.30, a first voltage source (V1) is provided on channel i and a secondvoltage source (V2) is provided on channel j. The DUT resistance canthen be determined based on the two source voltages and the terminationresistance Rt.

With reference to FIG. 31, a system block diagram of a portion of switchcard 2802 (FIG. 28) is depicted. As depicted in FIG. 31, switch card2802 (FIG. 28) includes a plurality of pin terminator circuits 3102. Inthe present exemplary embodiment, each switch card 2802 (FIG. 28)includes 32 pin terminator circuits 3102, where each pin terminatorcircuit 3102 is connected to a pin from probe card 2706.

As also depicted in FIG. 31, switch card 2802 (FIG. 28) includes aplurality of digital multiplexer (MUX) controls 3104. In the presentexemplary embodiment, each switch card 2802 (FIG. 28) includes 16digital MUX controls 3104, where each digital MUX control 3104 isconnected to two pin terminator circuits 3102 and provide eight controlsignals to each pin terminator circuits 3102.

With reference to FIG. 32, a circuit diagram of a portion of pinterminator circuit 3102 (FIG. 31) is depicted. As depicted in FIG. 32,pin terminator circuit 3102 (FIG. 31) includes a plurality of quadswitches 3202. In the present exemplary embodiment, each terminatorcircuit 3102 (FIG. 31) includes two quad switches 3202, where each quadswitch 3202 is connected to a source voltage and four control signals.Thus, quad switches 3202 can connect the pin connected to pin terminatorcircuit 3102 (FIG. 31) to any of the source voltages and controlsignals.

With reference to FIG. 33, a system block diagram of MC unit 2306 isdepicted. As described above, MC unit 2306 includes multiplexer module2710 (FIG. 27), which receives test signals from probe card 2706 (FIG.27). In the present exemplary embodiment, multiplexer module 2710 (FIG.27) includes a plurality of multiplexer cards 3302 to combine the testsignals received from probe card 2706 (FIG. 27). More particularly, asdepicted in FIG. 28, each multiplexer card 3302 is a 32-to-1 analogmultiplexer card that combines 32 channels received from probe card 2706(FIG. 27) into one DAQ channel. In the present exemplary embodiment,eight multiplexer cards 3302 are used to combine the 256 test signalsinto eight DAQ channels, which are transmitted to an eight channel DAQcard 3304, which converts analog input to 16 bit digital measurements.In the present exemplary embodiment, DAQ card 3304 uses only one of theeight DAQ channels at a time.

As depicted in FIG. 33, multiplexer cards 3302 are connected to a signalconditional extensions for instrumentation (SCXI) bus 3306. DAQ card3304 is connected to a PCI bus 3308. SCXI bus 3306 and PCI bus 3308 areconnected to a local bus 3310.

As also depicted in FIG. 33, MC unit 2306 includes a digital I/O card3312 with DIGIO 2712 to send control signals to pin termination unit2314 (FIG. 27). More particularly, digital I/O card 3312 generatesaddress, data, and control signals used to configure pin terminationunit 2314 (FIG. 27). The address and data are decoded by terminationunit 2314 (FIG. 27) to select a termination resistor, voltage source,ground, or open circuit for each probe pin on probe card 2706 (FIG. 27).

MC unit 2306 also includes PCI bridge 2714 and a voltage source 3314,which outputs 16 voltage sources to pin termination unit 2314 (FIG. 27)using a VSX 3316. PCI bridge 2714 and voltage source 3314 are bothconnected to PCI bus 3308.

IV. Analysis

The results of the electrical test can be analyzed to identify thelocation of (i.e., localize) any defects. More specifically, thelocation of a test structure failing the electrical test is determinedbased on the results of the electrical test. The results of theelectrical test also can be analyzed to classify detected defects asrandom or systematic defects. Furthermore, the results can be analyzedto determine, model, or predict a yield.

With reference to FIG. 34, an exemplary process of defect analysis isdepicted. In the present exemplary process, test chip design patterns3402 are grouped into layout bins (e.g., bins 1-9 as depicted in FIG.34). As depicted in FIG. 34, the test chip is fabricated andelectrically tested (3404). Failure counts for each layout bin are thenplotted (3406).

With reference to FIG. 35, an exemplary plot of failure rate vs. layoutbins (e.g., VSTK, VNBH, VP, VBD, VLE, VBC, and VC) is depicted. The plotof failure rate vs. layout bins provides a first order indication ofpattern dependency in test chip failures. With reference to FIG. 36,adding process margin splits to the plot provide a first orderindication of process margin dependency in test chip failures.

With reference to FIG. 37, in one exemplary embodiment, a systematicdefect identifier algorithm can analyze the test data vs. layout DOEfactors (including process margin variants) and automatically identifypatterns with statistically higher fail rate. As also depicted in FIG.37, a summary of systematic vs. random fail rates can be shown in a barchart format with systematic failures highlighted to the user throughsummary bar charts.

Another approach to classifying defects as random or systematic defectsand predicting yield is described in U.S. Pat. No. 6,449,749, entitledSYSTEM AND METHOD FOR PRODUCT YIELD PREDICTION, issued on Sep. 10, 2002,which is incorporated herein by reference in its entirety. It should berecognized, however, that defects can be classified and yield can bemodeled using various approaches.

V. SEM Inspection Tool

As described above, the results of the analysis can be used to localizethe defects using an inspection tool. When an inspection tool is used,the test chip is adapted for use with the inspection tool by sizing thetest structures to be compatible with the capabilities of the inspectiontool.

For example, in one exemplary embodiment, the inspection tool is aSEMVision G2 tool produced by Applied Materials, Inc. of Santa Clara,Calif. USA. Thus, the test chip is adapted for use with the SEMVision G2tool. More specifically, the test structures on the test chip are sizedto be compatible with the view field and resolution of the SEMVision G2tool.

Although exemplary embodiments have been described, variousmodifications can be made without departing from the spirit and/or scopeof the present invention. Therefore, the present invention should not beconstrued as being limited to the specific forms shown in the drawingsand described above.

1. A method for fast localization of electrically measured defects ofintegrated circuits, comprising: (a) obtaining a test chip fabricated tohave test structures configured for parallel electrical testing; (b)electrically testing the test structures on the test chip employing aparallel electrical tester; and (c) analyzing results of the electricaltesting to localize defects on the test chip.
 2. The method of claim 1,further comprising: inspecting the localized defects on the test chipusing an inspection tool.
 3. The method of claim 2, wherein theinspection tool is a scanning electron microscope (SEM).
 4. The methodof claim 3, further comprising: sizing the test structures on the testchip to be compatible with a view field of the SEM.
 5. The method ofclaim 1, further comprising: grouping the test structures into one ormore padgroups, wherein the test structures in a padgroup areelectrically tested together in parallel.
 6. The method of claim 5,wherein a padgroup includes: two columns of test structures; and twocolumns of pads disposed between the two columns of test structures. 7.The method of claim 5, further comprising: grouping padgroups into oneor more sticks, wherein the padgroups in a stick are electrically testedtogether in parallel.
 8. The method of claim 7, wherein the padgroups ina stick are electrically tested together in parallel using a probe cardconnected to the parallel electrical tester.
 9. The method of claim 8,wherein one or more cells having test structures and corresponding padsare disposed between two padgroups in a stick, wherein the one or morecells are used to verify the operation of the probe card.
 10. The methodof claim 7, further comprising: stacking two or more sticks together ina layout.
 11. The method of claim 10, further comprising: adjusting thenumber of sticks stacked together in the layout to fit within a scannerfield.
 12. The method of claim 1, further comprising: in-line inspectingthe test chip using an optical inspection tool.
 13. The method of claim1, wherein the test chip includes a plurality of design patternvariations.
 14. The method of claim 1, wherein the test structures aretwo-terminal or four-terminal test structures.
 15. The method of claim1, wherein one of the test structures is a snakecomb cell configured tolocalize a defect in the snakecomb cell to a location within thesnakecomb cell.
 16. The method of claim 1, wherein electrically testingincludes: comparing a line resistance to a first threshold resistance,wherein the line resistance is determined based on a measured voltage;when the line resistance is below the first threshold voltage, detectinga soft short; comparing the line resistance to a second thresholdresistance; and when the line resistance is below the second thresholdresistance, detecting a hard short, wherein the first thresholdresistance is greater than the second threshold resistance.
 17. Themethod of claim 1, wherein electrically testing includes: determining anaverage resistance for a number of lines adjacent to each other;comparing a line resistance to the average resistance; when the lineresistance is less than the average resistance by a first specifiedamount, detecting a soft short; and when the line resistance is lessthan the average resistance by a second specified amount, detecting ahard short, wherein first specified amount is less than the secondspecified amount.
 18. The method of claim 1, wherein the parallelelectrical tester is connected to a wafer loader and a wafer prober, andfurther comprising: loading one or more test chips from the wafer loaderinto the wafer prober to be tested, and wherein the wafer proberincludes a probe card to electrically contact the test structures on thetest chip to be electrically tested in parallel.
 19. The method of claim18, further comprising: transmitting test signals between the probe cardand a pin termination module in the parallel electrical tester;transmitting test signals between the pin termination module and ameasurement control module in the parallel electrical tester; andtransmitting. commands to the wafer prober from a tester control modulein the parallel electrical tester.
 20. The method of claim 19, furthercomprising: transmitting voltage sources and control signals from themeasurement control module to the pin termination module.
 21. The methodof claim 19, further comprising: receiving test signals from the probecard at a plurality of switch cards in the pin termination module,wherein each switch card is connected to a group of pins from the probecard.
 22. The method of claim 21, wherein a switch card forms a resistordivider with a resister in a test structure, a termination resistor, anda voltage source.
 23. The method of claim 21, wherein a switch cardincludes: a plurality of pin terminator circuits, wherein each pinterminator circuit is connected to a pin from the probe card; and aplurality of digital multiplexer controls, wherein each digitalmultiplexer control is connected to two pin terminator circuits.
 24. Themethod of claim 23, wherein a pin terminator circuit includes aplurality of quad switches, wherein each quad switch is connected to avoltage source and control signals.
 25. The method of claim 19, furthercomprising: receiving test signals from the probe card at a multiplexermodule in the measurement control module; combining a set of testsignals received from the probe card into a digital acquisition signal;and transmitting the digital acquisition signal to a digital acquisitioncard.
 26. The method of claim 1, wherein analyzing results comprises:classifying detected defects as random or systematic defects.
 27. Themethod of claim 26, further comprising: grouping test chip designpatterns into layout bins; and plotting failure counts for each layoutbin.
 28. A system for fast localization of electrically measured defectsof integrated circuits, comprising: (a) a test chip having teststructures configured to be parallel electrically tested; (b) a parallelelectrical tester configured to parallel electrically test the teststructures on the test chip; and (c) a processor configured to analyzeresults from the parallel electrical tester to localize defects on thetest chip.
 29. The system of claim 28, further comprising: an inspectiontool configured to inspect the localized defects on the test chip. 30.The system of claim 29, wherein the inspection tool is a scanningelectron microscope (SEM).
 31. The system of claim 30, wherein the teststructures on the test chip are sized to be compatible with a view fieldof the SEM.
 32. The system of claim 28, wherein the test structures aregrouped into one or more padgroups, wherein the test structures in apadgroup are electrically tested together in parallel.
 33. The system ofclaim 32, wherein a padgroup includes: two columns of test structures;and two columns of pads disposed between the two columns of teststructures.
 34. The system of claim 32, wherein padgroups are groupedinto one or more sticks, wherein the padgroups in a stick areelectrically tested together in parallel.
 35. The system of claim 34,wherein the padgroups in a stick are electrically tested together inparallel using a probe card connected to the parallel electrical tester.36. The system of claim 35, wherein one or more cells having teststructures and corresponding pads are disposed between two padgroups ina stick, wherein the one or more cells are used to verify the operationof the probe card.
 37. The system of claim 34, wherein two or moresticks are stacked together in a layout.
 38. The system of claim 37,wherein the number of sticks stacked together in the layout is adjustedto fit within a scanner field.
 39. The system of claim 28, furthercomprising: an optical inspection tool to in-line inspect the test chip.40. The system of claim 28, wherein the test chip includes a pluralityof design pattern variations.
 41. The system of claim 28, wherein thetest structures are two-terminal or four-terminal test structures. 42.The system of claim 28, wherein one of the test structures is asnakecomb cell configured to localize a defect in the snakecomb cell toa location within the snakecomb cell.
 43. The system of claim 28,wherein test structures are placed at more than one level.
 44. Thesystem of claim 43, wherein test structure below a test structure onanother level is electrically tested.
 45. The system of claim 43,wherein the interaction of test structures at two different levels ismeasured.
 46. The system of claim 28, wherein the parallel electricaltester is configured to: compare a line resistance to a first thresholdresistance, wherein the line resistance is determined based on ameasured voltage; when the line resistance is below the first thresholdvoltage, detect a soft short; compare the line resistance to a secondthreshold resistance; and when the line resistance is below the secondthreshold resistance, detect a hard short, wherein the first thresholdresistance is greater than the second threshold resistance.
 47. Thesystem of claim 28, wherein the parallel electrical tester is configuredto: determine an average resistance for a number of lines adjacent toeach other; compare a line resistance to the average resistance; whenthe line resistance is less than the average resistance by a firstspecified amount, detect a soft short; and when the line resistance isless than the average resistance by a second specified amount, detect ahard short, wherein first specified amount is less than the secondspecified amount.
 48. The system of claim 28, wherein the parallelelectrical tester is connected to a wafer loader and a wafer prober,wherein the wafer loader loads one or more test chips into the waferprober to be tested, and wherein the wafer prober includes a probe cardto electrically contact the test structures on the test chip to beelectrically tested in parallel.
 49. The system of claim 48, wherein theparallel electrical tester includes: a pin termination module connectedto the probe card, wherein test signals are transmitted between the pintermination module and the probe card; a measurement control moduleconnected to the pin termination module, wherein test signals aretransmitted between the pin termination module and the measurementcontrol module; and a tester control module connected to the measurementcontrol module and the wafer prober, wherein the tester control modulesends commands to the wafer prober.
 50. The system of claim 49, whereinthe measurement control module provides voltages source and controlsignals to the pin termination module.
 51. The system of claim 48,wherein the pin termination module includes: a plurality of switch cardsto receive test signals from the probe card, wherein each switch card isconnected to a group of pins from the probe card.
 52. The system ofclaim 48, wherein a switch card forms a resistor divider with a resisterin a test structure, a termination resistor, and a voltage source. 53.The system of claim 51, wherein a switch card includes: a plurality ofpin terminator circuits, wherein each pin terminator circuit isconnected to a pin from the probe card; and a plurality of digitalmultiplexer controls, wherein each digital multiplexer control isconnected to two pin terminator circuits.
 54. The system of claim 53,wherein a pin terminator circuit includes a plurality of quad switches,wherein each quad switch is connected to a voltage source and controlsignals.
 55. The system of claim 49, wherein the measurement controlmodule includes: a multiplexer module that receives test signals fromthe probe card; and a digital acquisition card, wherein the multiplexermodule combines a set of test signals received from the probe card intoa digital acquisition signal sent to the digital acquisition card. 56.The system of claim 28, wherein the processor is configured to: classifydetected defects as random or systematic defects.
 57. The system ofclaim 56, wherein the processor is configured to: group test chip designpatterns into layout bins; and plot failure counts for each layout bin.58. A computer-readable storage medium containing computer executablecode to instruct a computer to localize electrically measured defects ofintegrated circuits by instructing the computer to operate as follows:obtaining a test chip fabricated to have test structures configured forparallel electrical testing; electrically testing the test structures onthe test chip employing a parallel electrical tester; and analyzingresults of the electrical testing to localize defects on the test chip.